13.2 The ADC clock

The successive approximation nature of the ADC (used in the ATMega128) requires its own clock. Instead of using another oscilator that is asynchronous to the system clock, the ATMega128 allows software to configure the ADC clock based on the main clock. This is documented on page 232 of the ATMega128 datasheet.

The prescaler is controled by ADPS0-ADPS2, bits 0 to 2 of I/O location ADCSRA. The exact division factor is shown on page 244 of the datasheet. Note that a high speed ADC clock cannot fully utilize the 10-bit resolution capable of the device.