With a reflow oven, this does not pose any problem because the solder paste placed under the chip will flow as the temperature increases.However, for hand soldering, it is much more difficult to get solder under a chip to flow.
This is why I included four large vias under the chip. A find soldering tip should fit in such a via, and so we can solder the chip at least to the vias. This design also allows me to put a large pad on the top side for additional heatsinking.
As far as the traces are concerned, the current (20040322) layout has two main ``trunks'' for ground and supply. The design is also chainable, making it easy to add three more H-bridges without adding to ground and power routing problems. The relatively large ground and supply traces also provide additional heatsinking resources.
Because of the use of a PAL/CPLD, routing control signals is easier (than without a PAL/CPLD). As long as the PAL/CPLD is placed between the MCU and the H-bridges, I can use APL/CPLD equations as routing resources.
Copyright © 2006-02-15 by Tak Auyeung